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vendor/scrivo/highlight.php/test/detect/verilog/default.txt

@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+
+/**
+ * counter: a generic clearable up-counter
+ */
+
+module counter
+    #(parameter WIDTH=64, NAME="world")
+    (
+        input clk,
+        input ce,
+        input arst_n,
+        output reg [WIDTH-1:0] q
+    );
+    
+    string name = "counter";
+    localparam val0 = 12'ha1f;
+    localparam val1 = 12'h1fa;
+    localparam val2 = 12'hfa1;
+
+    // some child
+    clock_buffer #(WIDTH) buffer_inst (
+      .clk(clk),
+      .ce(ce),
+      .reset(arst_n)
+    );
+
+    // Simple gated up-counter with async clear
+
+    always @(posedge clk or negedge arst_n) begin
+        if (arst_n == 1'b0) begin
+            q <= {WIDTH {1'b0}};
+            end
+        else begin
+            q <= q;
+            if (ce == 1'b1) begin
+                q <= q + 1;
+            end
+        end
+    end
+
+    function int add_one(int x);
+      return x + 1;
+    endfunction : add_one
+
+`ifdef SIMULATION
+initial $display("Hello %s", NAME);
+`endif
+endmodule : counter
+
+class my_data extends uvm_data;
+  int x, y;
+
+  function add_one();
+    x++;
+    y++;
+  endfunction : add_one
+endclass : my_data